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Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 2 LVCMOS / LVTTL outputs * LVCMOS / LVTTL clock input accepts LVCMOS or LVTTL input levels * Maximum output frequency: 200MHz * Output skew: 25ps (typical) * Part-to-part skew: 250ps (typical) * Small 8 lead SOIC package saves board space * Full 3.3V or 3.3V core, 2.5V supply modes * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8302 is a low skew, 1-to-2 LVCMOS/ LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClock STM family of High Performance Clock Solutions from ICS. The ICS8302 has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8302 features a pair of LVCMOS/LVTTL outputs. The I C S 8 3 0 2 i s c h a r a c t e r i ze d a t f u l l 3 . 3 V for input VDD , and mixed 3.3V and 2.5V for output operating supply m o d e s (V DDO ). G u a r a n t e e d o u t p u t a n d p a r t - t o - p a r t skew characteristics make the ICS8302 ideal for clock distribution applications demanding well defined performance and repeatibility.
ICS
BLOCK DIAGRAM
Q0 CLK Q1
PIN ASSIGNMENT
VDDO VDD CLK GND 1 2 3 4 8 7 6 5 Q0 GND VDDO Q1
ICS8302
8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
Type Power Power Input Power Output Output Pulldown Description Output supply pins. Core supply pin. LVCMOS / LVTTL clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 6 2 3 4,7 5 8 Name VDDO VDD CLK GND Q1 Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pulldown Resistor Output Impedance 5 VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V Test Conditions Minimum Typical 4 22 16 51 7 12 Maximum Units pF pF pF k
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Power Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 13 4 Units V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK CLK VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 50 to VDDO/2 IOH = -100A 50 to VDDO/2 IOL = 100A -5 2.6 2.9 0.5 0.2 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A V V V V
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time Output Duty Cycle 20% to 80% 20% to 80% 133MHz 300 300 45 200MHz 1.9 2.35 25 250 Test Conditions Minimum Typical Maximum 200 2.8 85 800 800 800 55 Units MHz ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF odc
133MHz < 200MHz 40 60 % Parameters measured at fMAX unless otherwise noted. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 13 4 Units V V mA mA
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK CLK VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 50 to VDDO/2 IOH = -100A 50 to VDDO/2 IOL = 100A -5 1.8 2.2 0.5 0.2 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A V V V
V
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time Output Duty Cycle 20% to 80% 20% to 80% 133MHz 133MHz < 200MHz 250 250 45 40 250 200MHz 2.3 Test Conditions Minimum Typical Maximum 200 3.3 85 800 650 650 55 60 Units MHz ns ps ps ps ps % %
tsk(o) tsk(pp)
tR tF odc
Parameters measured at fMAX unless otherwise noted. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD VDDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1 Qx
V
DD
V
DDO
2
Qx
2
PART 2 Qy
V
DD
V
DDO
2 tsk(pp)
Qy
2 tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
80% 20% tR
80%
CLK
VDD 2
Clock Outputs
20% tF
Q0, Q1
t
PD
VDDO 2
OUTPUT RISE/FALL TIME
VDDOX VDDOX 2 t PW t PERIOD VDDOX 2
PROPAGATION DELAY
Q0, Q1
2
odc =
t PW t PERIOD
OUTPUT PULSE WIDTH/PERIOD
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8302 is: 322
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
Marking 8302AM 8302AM 8302AMLF 8302AMLF Package 8 lead SOIC 8 lead SOIC 8 lead "Lead Free" SOIC 8 lead "Lead Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS8302AM ICS8302AMT ICS8302AMLF ICS8302AMLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8302AM
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REV. D MAY 17, 2005
Integrated Circuit Systems, Inc.
ICS8302
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Pin Description table, revised VDD description. Pin Characteristics table, deleted RPULLUP row. Power Supply table, changed VDD parameter to correspond with description. AC Characteristics tables - added note "Parameters measured at fMAX unless otherwise noted." tpLH Test Conditions, added f 200MHz. Pin Chararcteristics table - changed CIN 4pF max. to 4pF typical. Added 5 min. and 12 max. to ROUT row. Ordering Information table - added "Lead-Free" par t number. LVCMOS DC Characteristics Table - changed VIL max. from 1.3V to 0.8V. Ordering Information Table - added Lead-Free note. Date
Rev
B
Table T1 T2 T3A & T3C T4A & T4B
Page 2 2 3, 4 3, 4
2/4/03
T2 C T7 T3B & T3D T7
2 8 3, 4 8
6/15/04
D
5/17/05
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REV. D MAY 17, 2005

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